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With integrated tungsten buried power rails.
June 15, 2020
By: Anthony Locicero
Copy editor, New York Post
At the 2020 Symposia on VLSI Technology and Circuits, imec presented a tungsten (W) buried power rail (BPR) integration scheme in a FinFET CMOS test vehicle, which does not adversely impact the CMOS device characteristics. When interfacing the BPR with Ru M0A lines through a Ru via contact, excellent resistance values and electromigration behavior have been measured. A complimentary assessment study shows the advantages at the system level of implementing BPRs as a scaling booster in 3 nm...
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